TSMC's business model is deceptively simple in concept and extraordinarily complex in execution. The company operates exclusively as a contract manufacturer of semiconductors — it does not design chips, it does not sell chips under its own brand, and it does not compete with its customers. Every dollar of revenue TSMC earns comes from charging customers a fee to manufacture chips according to those customers' proprietary designs. This pure-play foundry model, which Morris Chang essentially invented in 1987, has proven to be one of the most durable and profitable industrial structures ever created. The revenue architecture is organized around manufacturing process nodes, each representing a generation of fabrication technology defined by the minimum feature size achievable on a silicon wafer. In fiscal 2024, TSMC's advanced nodes — defined by the company as 7-nanometer and below — generated the overwhelming majority of revenue. The 3-nanometer node, which began volume production in late 2022 and ramped aggressively through 2023 and 2024, accounted for approximately 18 to 20 percent of wafer revenue by the fourth quarter of 2024, driven almost entirely by Apple's A17 Pro chip for the iPhone 15 Pro lineup and Apple's M3 processor family. The 5-nanometer node, which houses NVIDIA's most commercially significant AI GPU products as well as AMD's high-end Ryzen and EPYC processors, contributed approximately 35 percent of wafer revenue across 2024. Together, these two nodes — 3-nanometer and 5-nanometer — represented more than half of all TSMC revenue, a remarkable concentration that reflects the winner-take-most dynamics of advanced semiconductor manufacturing. The pricing structure in semiconductor foundry is fundamentally different from other contract manufacturing industries. TSMC charges customers on a per-wafer basis, with prices increasing dramatically as process nodes advance. A single 300-millimeter wafer manufactured at the 3-nanometer node costs approximately $20,000 to $25,000, compared with roughly $10,000 to $12,000 for a 7-nanometer wafer and perhaps $3,000 to $4,000 for a 28-nanometer wafer. The economics are justified by the extraordinary capital expenditure required to build and operate leading-edge fabs. TSMC's capital expenditure in 2024 was approximately $30 billion, a figure that has averaged over $25 billion annually for the past five years. Each new fab costs $15 billion to $20 billion to construct, and the machinery inside — extreme ultraviolet lithography systems from ASML that cost $200 million each — must be purchased, installed, calibrated, and maintained by engineers who spend years mastering the processes. Customer concentration is a defining feature of TSMC's revenue model. Apple is consistently the company's single largest customer, typically contributing 20 to 25 percent of annual revenue. In 2024, Apple's share was estimated at approximately 25 percent, reflecting the migration of all Apple silicon products — iPhone, Mac, iPad, and Apple Watch — to TSMC's most advanced nodes. NVIDIA surged to become the second-largest customer, with its share of TSMC revenue estimated to have climbed from roughly 6 percent in 2022 to approximately 11 to 13 percent by late 2024, driven by H100 and H200 GPU demand from AI data centers. AMD, Qualcomm, Broadcom, and MediaTek round out the top-tier customer base, each contributing 5 to 10 percent of revenue. Beyond wafer revenue, TSMC generates meaningful ancillary income through advanced packaging services. CoWoS — Chip on Wafer on Substrate — is TSMC's proprietary high-bandwidth interposer packaging technology that connects multiple chips on a single substrate with extremely dense interconnects. CoWoS is essential for NVIDIA's HBM memory-stacked GPU packages and AMD's multi-chip processor designs. In 2024, CoWoS capacity became a genuine bottleneck for NVIDIA's H100 shipments, and TSMC announced major capacity expansions that tripled CoWoS output by end of 2024. Advanced packaging is expected to grow as a proportion of TSMC revenue as chiplet architectures — designs that disaggregate semiconductor functions across multiple dies — become the dominant approach to pushing past the physical limits of conventional scaling. Geographically, TSMC's revenue base skews heavily toward customers headquartered in North America, which accounted for approximately 68 to 70 percent of 2024 revenue, reflecting the dominance of U.S. Fabless companies as customers. Asia-Pacific customers, including MediaTek and various Chinese customers, contributed approximately 10 to 12 percent, while European customers including Infineon and NXP represented a smaller portion. The geographic distribution of manufacturing, however, remains overwhelmingly concentrated in Taiwan, which houses the company's most advanced fabs. TSMC's Arizona fabs, its Kumamoto, Japan fab (producing 28-nanometer to 12-nanometer chips in partnership with Sony and Denso), and its Nanjing, China facility together represent less than 10 percent of total wafer capacity as of 2024. The foundry model generates remarkable operating leverage because TSMC can spread enormous fixed costs — depreciation on fab equipment, process engineering labor, utility costs — across an ever-larger base of customer volumes. Once a fab is built and a process is qualified, the marginal cost of additional wafers is significantly lower than the average cost, enabling gross margins to expand as utilization rates improve. TSMC's gross margin for full-year 2024 reached approximately 53.2 percent, up from 54.4 percent in 2023 (which benefited from a different product mix) — a figure that compares favorably with many software companies and is extraordinary for a capital-intensive manufacturer. The operating margin for 2024 was approximately 42 to 43 percent. TSMC's long-term capacity agreements, in which customers commit to purchasing a minimum volume of wafers over multiple years in exchange for capacity guarantees, have become an increasingly important element of the business model. These agreements, signed with major customers including Apple and NVIDIA, provide revenue visibility while simultaneously funding new capacity construction. The structure effectively turns some of TSMC's capital expenditure risk into shared investment with customers who have strategic reasons to ensure TSMC's manufacturing capacity remains available to them.