Sean Lie

Sean Lie holds a rigorous technical background in advanced semiconductor architecture, having served as a hardware engineer at AMD and as the Chief Hardware Architect at SeaMicro. This highly specialized background in building complex, interconnected silicon architectures alongside Gary Lauterbach provided the exact engineering trust and technical foundation required to design the incredibly complex interconnect fabric of the Cerebras Wafer-Scale Engine.

Sean Lie is a co-founder and Chief Hardware Architect at Cerebras Systems. A prodigy in digital logic design, Lie architected the internal 2D mesh fabric of the Wafer-Scale Engine, connecting 900,000 independent AI processor cores with line-rate, low-latency inter-core communication. Lie invented the hardware-level defect tolerance algorithms that allow the WSE-3 to automatically route around flawed silicon dies during power-up, solving the yield problem that had baffled the global semiconductor industry for over four decades. Lie's architectural skill was central to overcoming the 50-year-old 'wafer yield impossibility' that destroyed previous semiconductor pioneers. By conceiving a hardware-level defect tolerance system featuring redundant cores and a reconfigurable 2D mesh, Lie ensured that microscopic silicon defects do not destroy the wafer. At Cerebras, Lie directs overall silicon microarchitecture, instruction set design, and next-generation packaging technologies with TSMC. (Exact birth year remains publicly undisclosed).