Micron Technology, Inc. vs Taiwan Semiconductor Manufacturing Company: Strategic Comparison

This in-depth comparison examines Micron Technology, Inc. and Taiwan Semiconductor Manufacturing Company across revenue, market value, business model, competitive positioning, and long-term growth strategy. Whether you are researching Micron Technology, Inc. on its own, evaluating Taiwan Semiconductor Manufacturing Company, or weighing the two companies side by side, the breakdown below highlights where each company leads and where the gap between Micron Technology, Inc. and Taiwan Semiconductor Manufacturing Company is widest.

On the headline numbers, Micron Technology, Inc. reports annual revenue of $32.0B against $90.0B for Taiwan Semiconductor Manufacturing Company, while their respective market capitalizations stand at $105.0B and $900.0B. Micron Technology, Inc. is headquartered in United States and Taiwan Semiconductor Manufacturing Company operates from Taiwan, and those different home markets shape how each company competes.

Micron Technology, Inc.: Micron Technology received $6.2 billion in direct subsidies and loans under the CHIPS and Science Act — more federal manufacturing support than any semiconductor company in US history at the time of announcement. The money is going to Clay, New York, where Micron is building a $100 billion semiconductor manufacturing campus that, when complete, will be the largest memory fabrication facility in the Western Hemisphere. That investment, made possible partly by federal subsidy and partly by the AI infrastructure buildout creating unprecedented demand for High Bandwidth Memory, defines what Micron is becoming. The company generated $25.11 billion in total revenue for fiscal year 2024 — a massive recovery from the $15.54 billion reported in FY2023, when one of the most severe memory market downturns in the industry's history compressed revenue by nearly 40%. CEO Sanjay Mehrotra leads an organization of 48,000 employees headquartered in Boise, Idaho, that manufactures both DRAM and NAND flash memory at the leading edge of process technology. Micron's HBM3E High Bandwidth Memory stacks deliver 30% better power efficiency than competing solutions from Samsung and SK Hynix — a critical advantage in AI data centers where thermal design power, not raw compute performance, is increasingly the binding constraint on cluster density. That efficiency advantage, combined with the company's position as the sole US-based producer of leading-edge DRAM, is the foundation of the market position Mehrotra is building. The company was founded in 1978 in Boise, Idaho, by Doug Pitman, Ward Parkinson, Joe Parkinson, Dennis Wilson, and Adam O'Kane — five engineers who started in a dentist's office with the intention of designing custom semiconductors. Micron survived the brutal consolidation of the DRAM industry through multiple downturns, including the 2013 acquisition of Elpida Memory from bankruptcy, which gave Micron the Japanese manufacturing capabilities that now underpin its leading-edge DRAM production.

Taiwan Semiconductor Manufacturing Company: TSMC manufactures roughly 90% of the world's most advanced semiconductors on an island 110 miles from the Chinese mainland. That geographic concentration — with no historical precedent in modern industrial infrastructure — makes Taiwan Semiconductor the single most strategically important manufacturing facility on Earth, a position that generates both $90 billion in annual revenue and a geopolitical risk profile that no diversification strategy can fully eliminate. The $900 billion market capitalization on $90 billion in fiscal 2024 revenue implies a ten-times revenue multiple. That premium reflects the company's position as the only entity capable of manufacturing the most advanced chips that power artificial intelligence systems, the latest generation of smartphone processors, and military electronics. ASML's High-NA EUV lithography machines — which cost approximately $380 million each and are required for post-2nm process nodes — are allocated to TSMC first, as ASML's largest customer. No competitor receives those machines before TSMC. The foundry model that Morris Chang invented in 1987 solved an industrial coordination problem that the semiconductor industry did not know it had. Before TSMC, every chip designer had to either build its own fabrication facility — an increasingly expensive proposition — or license manufacturing capacity from an integrated device manufacturer that was also a direct competitor. Chang separated design from manufacturing permanently, enabling an entire generation of fabless companies to emerge: Qualcomm, NVIDIA, AMD, Apple Silicon. Revenue has grown from $67.6 billion in fiscal 2023 to $90 billion in fiscal 2024 — a $22.4 billion increase in a single year driven primarily by AI chip demand. NVIDIA's H100 and successor GPU architectures are manufactured at TSMC, and the demand for those chips from hyperscale cloud providers has been running above TSMC's available capacity since mid-2023. The CoWoS advanced packaging technology became a specific bottleneck in 2023, prompting TSMC to triple capacity through 2024 to address approximately 18 months of backlogged demand.

Micron Technology, Inc. and Taiwan Semiconductor Manufacturing Company pursue distinct approaches to generating revenue, and understanding how each company operates is the foundation of any fair comparison between Micron Technology, Inc. and Taiwan Semiconductor Manufacturing Company.

Micron Technology, Inc. business model: Despite facing acute challenges, including the permanent loss of the Chinese smartphone market due to US export controls, the immense depreciation burden of its new US fabs, and the aggressive pricing tactics of Samsung and SK Hynix, Micron's fundamental business model remains structurally dominant in the high-performance computing segment. The pricing architecture for Micron's products is bifurcated between highly commoditized, spot-market pricing for legacy consumer memory, and negotiated, contract-based pricing for advanced-node enterprise and AI memory. Conversely, during a downcycle, the fixed depreciation and interest expenses rapidly consume cash reserves, forcing the company to slash capital expenditures and reduce wafer starts to stabilize pricing. The primary financial risk is the immense depreciation burden associated with its new US fab construction; as the New York and Idaho facilities come online in 2026 and 2027, the company will incur billions of dollars in new depreciation expenses that will require sustained high memory pricing and high use rates to absorb, creating a high break-even point that could result in significant losses if another memory downcycle occurs before the fabs reach full scale. Following the US Department of Commerce's imposition of severe semiconductor export bans in late 2022, and China's subsequent retaliatory cybersecurity review that banned Micron products from critical infrastructure in May 2023, Micron was forced to write down hundreds of millions of dollars in inventory specifically designed for Chinese customers and redirect that capacity to other global markets, often at discounted pricing. The founding philosophy was simple but audacious: to design and manufacture the most advanced, highest-density memory chips in the world, competing directly with the entrenched Japanese conglomerates like Toshiba, NEC, and Hitachi who were then dominating the global memory market with superior quality and aggressive pricing. These early adopters provided the critical feedback and validation that allowed Micron to refine its manufacturing processes and establish the company as the last surviving US memory manufacturer, a title it would defend through four decades of brutal price wars, technological shifts, and geopolitical crises.

Taiwan Semiconductor Manufacturing Company business model: TSMC's gross margins reached approximately 53 to 54 percent in the second half of 2024, figures that reflect not just manufacturing efficiency but genuine pricing power — a rare commodity in any industrial business. Every dollar of revenue TSMC earns comes from charging customers a fee to manufacture chips according to those customers' proprietary designs. The pricing structure in semiconductor foundry is fundamentally different from other contract manufacturing industries. TSMC charges customers on a per-wafer basis, with prices increasing dramatically as process nodes advance. With the highest volumes of advanced wafer production in the world, TSMC can amortize equipment and process development costs across more units than any competitor, achieving lower per-unit costs at equivalent pricing. These process advances keep TSMC at the forefront of manufacturing technology and maintain the pricing premium associated with leading-edge nodes. The funding structure was itself a deliberate statement of commitment: Taiwan's government through ITRI contributed approximately 48 percent, Dutch semiconductor company Philips contributed 27.5 percent (bringing technical credibility and access to process technology licenses), and the remainder came from private Taiwanese investors.

The durability of a company's moat often decides long-term winners. Here is how the competitive advantages of Micron Technology, Inc. stack up against those of Taiwan Semiconductor Manufacturing Company.

Micron Technology, Inc. competitive advantage: Because HBM requires significantly more wafer area per gigabyte than standard planar DRAM, and involves complex advanced packaging processes that yield lower output per wafer, the effective supply of HBM is constrained, allowing Micron to negotiate multi-year, fixed-price allocation agreements with hyperscalers that guarantee high gross margins regardless of broader memory market fluctuations. Under CEO Sanjay Mehrotra, the business has successfully pivoted its product mix toward High Bandwidth Memory (HBM3E) and advanced-node data center solutions, securing multi-year supply agreements with Nvidia and the world's largest hyperscalers to power the next generation of artificial intelligence accelerators. The company's competitive moat is anchored by its technological leadership in HBM power efficiency, its aggressive adoption of 1-beta and 1-gamma DRAM nodes, and the immense financial barriers to entry that protect the triopoly from new competition. The competitive dynamic between Micron and Samsung is defined by a battle for absolute scale and technological parity; Samsung possesses a massive revenue base and vertical integration advantage, producing its own logic chips, displays, and mobile devices, which allows it to consume a significant portion of its own memory production and absorb market downturns better than pure-play memory vendors. Micron's strategic response to the SK Hynix threat has been to aggressively accelerate its HBM3E development cycle, bypassing certain intermediate testing phases to bring its 8-high and 12-high stacks to market rapidly, while simultaneously using its 1-beta DRAM node leadership to offer superior die-level performance that compensates for SK Hynix's early packaging advantages. Micron's competitive advantage lies in its ability to prove superior power efficiency in HBM, higher bit density in DRAM, and the geopolitical security of US-based manufacturing, a value proposition that resonates powerfully with Western hyperscalers seeking to de-risk their supply chains from East Asian geopolitical tensions. The competitive moat is also defended through the sheer scale of the capital investment required to compete; with a single leading-edge fab costing over $15 billion, and the R&D required to master EUV lithography and 3D NAND stacking running into the billions annually, the financial barrier to entry ensures that the triopoly will remain intact for the foreseeable future, protecting Micron's long-term pricing power and market share. This power efficiency advantage is critical for AI data centers, where the thermal design power (TDP) of AI server racks is the primary bottleneck preventing the deployment of higher-density computing clusters; by delivering the same memory bandwidth with significantly less heat generation, Micron's HBM3E allows hyperscalers to pack more AI accelerators into existing facility footprints, creating a compelling economic value proposition that transcends simple per-gigabyte pricing. The second pillar of the competitive advantage is Micron's aggressive adoption of leading-edge DRAM nodes, specifically its 1-beta and 1-gamma technologies, which use advanced multi-patterning and selective EUV integration to achieve the highest bit density per wafer in the industry. In 1981, Micron emerged from stealth with the 64K DRAM, a product that was fundamentally competitive with the Japanese offerings, but which suffered from a significant cost disadvantage due to the sheer scale and efficiency of the Japanese mega-fabs.

Taiwan Semiconductor Manufacturing Company competitive advantage: The structural challenge Intel faces is that building competitive foundry capability requires the same decades of manufacturing culture, process optimization, and ecosystem development that TSMC has already accumulated. The convergence of the hyperscaler custom silicon boom with the AI infrastructure buildout has created a demand environment for advanced TSMC capacity that is, as of mid-2025, still characterized by more demand than supply at the leading edge. TSMC faces a cluster of structural challenges that are as serious as any confronted by a company of its scale and strategic importance. A weak iPhone cycle, a delay in NVIDIA's next GPU generation, or a shift in hyperscaler AI investment timing could materially impact TSMC's near-term revenue trajectory. TSMC's competitive advantage is best understood not as a single moat but as a series of reinforcing barriers that have compounded over nearly four decades into something approaching structural invulnerability at the leading edge of semiconductor manufacturing. The first and most fundamental advantage is process technology leadership. The ecosystem advantage is equally powerful. Over thirty-five years, TSMC has built an ecosystem of equipment suppliers, materials providers, electronic design automation tools, and intellectual property vendors that is specifically optimized around TSMC's process libraries and design rules. This ecosystem lock-in means that switching to a competitor foundry would require not just technical qualification work but a fundamental redesign of internal development workflows, often representing years of engineering time. Trust and confidentiality represent a surprisingly critical competitive advantage in the foundry business. Finally, TSMC's manufacturing scale creates cost advantages that are self-reinforcing. This scale also gives TSMC preferential access to equipment from vendors like ASML — TSMC receives the largest allocation of EUV machines of any foundry customer globally, giving it first-mover advantage on each new equipment generation. Demand for advanced semiconductor manufacturing capacity is virtually certain to grow as AI inference workloads scale, autonomous vehicles become commercialized, and next-generation smartphones and personal computing devices deploy increasingly sophisticated silicon. Small companies with promising chip designs but limited capital had essentially no path to manufacturing their products at competitive scale.

Future prospects matter as much as current results. The growth strategies below explain how Micron Technology, Inc. and Taiwan Semiconductor Manufacturing Company each plan to expand from here.

Micron Technology, Inc. growth strategy: This land-and-expand strategy within the data center is critical; as AI models grow from billions to trillions of parameters, the memory bandwidth required to prevent the GPU from starving for data increases exponentially, ensuring that Micron's content-per-server metrics continue to scale regardless of broader macroeconomic headwinds in the consumer electronics sector. The capital allocation strategy under CEO Sanjay Mehrotra has deliberately shifted away from pursuing maximum market share in low-margin consumer electronics, focusing instead on capturing the highest-value segments of the data center and AI markets. The land-and-expand strategy within the data center is driven by the exponential growth of AI model parameters; as large language models scale from hundreds of billions to trillions of parameters, the memory bandwidth required to prevent the GPU from idling increases proportionally, ensuring that Micron's content-per-server metrics continue to scale even if the total number of servers shipped remains flat. The overall business model is a masterclass in extreme industrial engineering: acquire the technological capability to print the smallest possible transistor and stack the highest possible number of 3D layers, expand revenue by capturing the most demanding AI and data center workloads, retain the customer through deep architectural integration and multi-year allocation agreements, and defend the margin through relentless yield optimization and government-subsidized capacity expansion. While US export controls have severely limited YMTC's access to advanced NAND equipment, CXMT continues to expand its domestic DRAM capacity, threatening to capture the low-end Chinese PC and smartphone markets that Micron was forced to abandon due to geopolitical restrictions. Micron counters this by completely exiting the commodity, low-margin segments and focusing exclusively on the high-performance, advanced-node segments where Chinese manufacturers lack the lithography tools and process expertise to compete, effectively ceding the bottom 20% of the market to protect the margins of the top 80%. This consolidation has fundamentally altered the competitive dynamics, replacing the destructive, market-share-at-all-costs price wars of the 1990s and 2000s with a more rational, profit-focused oligopoly where capacity discipline is prioritized over volume growth. The financial trajectory is characterized by a deliberate shift in product mix; the percentage of revenue derived from HBM and data center-centric products has grown from less than 10% in FY2022 to over 25% in FY2024, structurally elevating the company's long-term gross margin profile and reducing its exposure to the volatile consumer electronics cycle. SK Hynix, in particular, established an early lead in the HBM market by qualifying its HBM3 products for Nvidia's A100 accelerator, forcing Micron to invest heavily to catch up in HBM3E qualification, a race where being a single generation behind can result in losing the primary design win for the next decade of AI hardware. The fourth pillar is the deep, architectural integration with Nvidia and other AI chip designers; Micron's engineering teams work directly with Nvidia's architecture groups years in advance of product launches to co-design the custom PHY interfaces, thermal spreaders, and interposer routing required for HBM integration. Micron Technology's growth strategy is explicitly defined by the 'Advanced Node and AI Content' framework, a systematic initiative to capture specific market segments by deploying targeted technologies that expand the company's share of the AI server bill of materials (BOM) without relying on unit volume growth. The strategy is executed through the aggressive ramp of HBM3E and the development of HBM4, which will increase the memory content per AI accelerator from 80GB in the H100 to over 140GB in the H200 and beyond, ensuring that Micron's revenue grows in direct proportion to the performance capabilities of next-generation AI silicon. This growth strategy is executed through a land-and-expand motion that relies on deep architectural integration with Nvidia, AMD, and custom AI chip designers; rather than competing on price in the commodity market, the engineering team focuses on co-developing the custom PHY interfaces and thermal solutions required for next-generation HBM stacks, creating a level of technical lock-in that guarantees multi-year supply agreements and premium pricing. The channel partner strategy is also evolving to support this framework; Micron is training its network of global module makers and distribution partners to sell the advanced-node server DRAM and enterprise SSDs as comprehensive 'AI Infrastructure' packages, offering customers validated compatibility lists and performance benchmarks that justify the premium pricing of Micron's leading-edge products. The company is also pursuing strategic, tuck-in acquisitions to fill gaps in its advanced packaging and controller capabilities; recent investments in packaging startups and controller design firms are specifically targeted to enhance the HBM production yield and the performance of data center SSDs, providing customers with higher-reliability products without requiring the development of new foundational silicon technologies from scratch. The international growth strategy involves establishing a balanced, geographically diversified manufacturing footprint, using the $6.2 billion in CHIPS Act funding to build leading-edge DRAM capacity in the United States, while simultaneously expanding its advanced NAND and HBM packaging facilities in Singapore and Japan to maintain proximity to the Asian supply chain ecosystem and customer base. The growth strategy also includes the development of industry-specific memory solutions for automotive, industrial, and edge AI applications, which incorporate specialized software features and ruggedized hardware designs tailored to the specific operational requirements and longevity demands of each vertical. The financial target of this growth strategy is to increase the average selling price (ASP) per gigabyte across the entire product portfolio by 15% annually, a figure that will be driven entirely by the advanced-node product mix shift and the successful penetration of the AI server market, without requiring a proportional increase in the sales and marketing headcount. The transition to EUV lithography for 1-gamma and 1-delta DRAM is also a critical component of the growth strategy, allowing Micron to achieve the necessary bit density reductions to maintain its cost leadership and gross margin expansion in the face of intense competitive pressure from Samsung and SK Hynix. The company is aggressively expanding its total addressable market (TAM) by capitalizing on the exponential growth of AI training and inference workloads, which require exponentially more memory bandwidth and capacity than traditional cloud computing tasks. The introduction of HBM4, scheduled for volume production in 2026, is the cornerstone of this strategy; HBM4 will use a custom base die designed in partnership with logic foundries to integrate advanced compute capabilities directly into the memory stack, delivering unprecedented bandwidth and reducing the latency between the GPU and the memory, a critical requirement for training trillion-parameter models. The company's long-term financial model targets $40 billion in annual revenue by fiscal year 2028, a goal that requires maintaining a 15% compound annual growth rate (CAGR) while expanding gross margins to the mid-30% range through the operating leverage of the advanced-node product mix and the full absorption of the CHIPS Act subsidies. However, the structural shift toward AI-driven computing is irreversible, and Micron's technological leadership in HBM and advanced-node DRAM positions it to capture the majority of the memory content growth in the AI server market over the next decade. Micron Technology was conceived in the spring of 1978, when Ward Parkinson, a visionary engineer with deep experience in the semiconductor industry, realized that the emerging market for dynamic random-access memory (DRAM) presented an opportunity to build a world-class chip company in the United States, far away from the crowded, hyper-competitive landscape of Silicon Valley. The team operated out of a modest facility in Boise, focusing entirely on building the core architecture of the company's first product: a 64K DRAM chip that would use the most advanced n-channel MOS technology available.

Taiwan Semiconductor Manufacturing Company growth strategy: This is not market dominance in the conventional sense; it is something closer to a natural monopoly built on decades of compounding technical investment, workforce development, and manufacturing discipline. The economics are justified by the extraordinary capital expenditure required to build and operate leading-edge fabs. Advanced packaging is expected to grow as a proportion of TSMC revenue as chiplet architectures — designs that disaggregate semiconductor functions across multiple dies — become the dominant approach to pushing past the physical limits of conventional scaling. TSMC's Arizona fabs, its Kumamoto, Japan fab (producing 28-nanometer to 12-nanometer chips in partnership with Sony and Denso), and its Nanjing, China facility together represent less than 10 percent of total wafer capacity as of 2024. Once a fab is built and a process is qualified, the marginal cost of additional wafers is significantly lower than the average cost, enabling gross margins to expand as use rates improve. The structure effectively turns some of TSMC's capital expenditure risk into shared investment with customers who have strategic reasons to ensure TSMC's manufacturing capacity remains available to them. Intel's foundry ambitions were articulated as a core element of the IDM 2.0 strategy — Intel Design and Manufacture, integrating internal chip design with external foundry services. Money can accelerate progress; it cannot buy thirty-five years of compounded manufacturing learning. This is theoretically possible but practically prohibitive: building and operating a leading-edge fab requires not just capital but a generation of accumulated manufacturing knowledge that even trillion-dollar companies cannot shortcut. The competitive dynamics are also being reshaped by the AI investment cycle in ways that benefit TSMC more than any other participant. NVIDIA's dominance of AI GPU markets has made TSMC its exclusive manufacturing partner, and the extraordinary economics of AI infrastructure — where a single H100 GPU commands $25,000 to $40,000 at retail while costing TSMC perhaps $3,000 to $5,000 in wafer costs — generate compelling economics across the supply chain. Moving from 3-nanometer to 2-nanometer to 1.4-nanometer processes requires not just incremental investment but generational leaps in equipment sophistication and process complexity. TSMC's growth strategy rests on three pillars that have remained remarkably consistent across management transitions and business cycles. The first is relentless process technology leadership: investing ahead of demand to ensure that when customers need the next generation of manufacturing capability, TSMC is the only credible option. The company's roadmap through 2-nanometer, A16, and eventually 1-nanometer-class processes (internally designated N1) represents a manufacturing technology pipeline that should sustain TSMC's leading-edge premium for at least the next decade. This government partnership model allows TSMC to expand geographic footprint without bearing the full incremental cost burden of manufacturing in higher-cost geographies. The third pillar is advanced packaging technology as a growth vector in its own right. Advanced packaging capacity expansion represented a major strategic investment in 2024 and 2025, with TSMC building dedicated packaging facilities in Taiwan to address the CoWoS bottleneck that constrained NVIDIA GPU shipments through 2023 and much of 2024. The key growth driver remains AI infrastructure: NVIDIA's Blackwell GPU architecture (manufactured at TSMC's 4-nanometer node), Apple's continued advancement of its silicon roadmap, and the proliferation of custom AI silicon across the hyperscaler community all point toward sustained strong demand for TSMC's most advanced manufacturing capacity through at least 2027. He spent a brief and reportedly unsatisfying period at General Instrument before receiving a call that would define his legacy: an offer to lead the Industrial Technology Research Institute (ITRI) in Taiwan, and to develop a strategy for building a semiconductor industry on the island. They either partnered with large integrated companies, which often meant giving up strategic control, or they struggled to raise enough capital to build their own factories, which distracted from the core engineering work of designing better chips. In exchange, customers would access world-class manufacturing without the capital burden of building their own fabs. The Philips partnership was particularly critical — it gave TSMC access to CMOS process technology that would have taken years to develop independently and provided a degree of international legitimacy that helped attract the company's first external customers. The earliest days were marked by the unglamorous work of building manufacturing capability from scratch. TSMC's first fab, Fab 1 in Hsinchu, was a converted building that produced chips on 6-inch wafers using 2-micron process technology — sophisticated by the standards of 1987 Taiwan but not at the absolute frontier. The company's first major external customer was a small American chip design company that needed manufacturing capacity it could not afford to build internally.

A closer look at the financial trajectory of Micron Technology, Inc. and Taiwan Semiconductor Manufacturing Company rounds out the comparison.

Micron Technology, Inc.: Revenue collapsed from $30.76 billion in FY2022 to $15.54 billion in FY2023 — a 49% decline in a single fiscal year driven by the most severe DRAM and NAND price collapse in over a decade. Recovery to $25.11 billion in FY2024 was driven by AI-related HBM demand and a gradual normalization of DRAM pricing as industry-wide supply cuts took effect. FY2025 revenue is projected at $32 billion, implying continuation of the recovery. Net income of $775 million in FY2024 was modest given the revenue recovery, reflecting the margin compression that accompanies a deep inventory correction and the depreciation burden of the company's capital-intensive manufacturing footprint. Memory manufacturing requires over $8 billion in annual R&D and capital expenditure just to maintain leading-edge technology nodes — a cost structure that crushes profitability during downturns and generates exceptional returns when prices recover. Market capitalization of $105 billion against FY2024 revenue of $25.11 billion reflects the projected HBM and AI data center revenue trajectory rather than trailing earnings. Micron's 1-beta DRAM node achieves the highest bit density per wafer in the industry, structurally lowering cost-of-goods-sold and providing a margin buffer during the inevitable next downcycle. That cost advantage is the financial foundation of the company's ability to survive memory market cycles that have killed every American DRAM competitor except Micron. The $6.2 billion in CHIPS Act funding transforms the Clay, New York, fab from a long-range possibility into a near-term capital commitment. When complete, it will give Micron domestic manufacturing capacity that does not depend on facilities in Taiwan or Japan — a geopolitical risk management decision as much as a strategic one.

Taiwan Semiconductor Manufacturing Company: TSMC earned $35 billion in net income on $90 billion in fiscal 2024 revenue — a 38.9% net margin that is extraordinary for any manufacturing company and that reflects genuine pricing power rather than accounting artifact. Gross margins ran at 53-54% in the second half of 2024. A company with $90 billion in revenue and a 39% net margin is generating earnings that most software companies with ten times the revenue cannot match. Revenue growth has been dramatic: $57.7 billion in fiscal 2021, $75.9 billion in fiscal 2022, a decline to $67.6 billion in fiscal 2023 as semiconductor demand corrected from pandemic-era overordering, and then $90 billion in fiscal 2024 as AI chip demand overwhelmed the correction. The $22.4 billion single-year increase from fiscal 2023 to fiscal 2024 is larger than the total annual revenue of most semiconductor companies. The Arizona fab investment has expanded from the initial $12 billion announcement to over $65 billion — the largest single manufacturing investment in American history. That capital commitment has been driven by US government incentives under the CHIPS Act and by customer pressure from Apple, NVIDIA, and AMD to maintain a manufacturing presence in the United States as a hedge against Taiwan-related supply disruption. The per-wafer cost at Arizona fabs will initially be higher than Taiwan operations, but TSMC has demonstrated that it can close cost gaps over time as yields improve and operations mature. The $900 billion market capitalization places TSMC at ten times fiscal 2024 revenue. That valuation has a specific basis: the company manufactures something that no other entity can manufacture at comparable volume, quality, or process sophistication, and demand for that something is growing faster than TSMC can build capacity. The geopolitical discount — which markets apply to the Taiwan concentration risk — is offset by the AI demand premium, producing a net valuation that reflects both the opportunity and the risk simultaneously.